Location: Gurgaon/Gurugram
Salary: Open
Employment Type: Permanent

Company Overview

Leading product based company

Job Description

5-12 years of experience


Be able to write RTL code with System VerilogHDL
Be able to synthesis RTL design and analyze its timing report
Have an experience with designing an IP with on-chip interconnect protocol like AXI or AHB.
Have an experience with designing an IP with interface or protocol : PCIe, ONFI or Toggle, NVMe, DDR
Have an experience with Formal Property Verification
Experience with ECO flow


Deep understand issues with Coherency and Atomicity in system.
Communication and documentation skill
Experience with any Git framework

Job reference: JO-201126-230391

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