Staff Engineer - ASIC IP Logic Design

Leading product based company

5-12 years of experience

Mandatory

Be able to write RTL code with System VerilogHDL
Be able to synthesis RTL design and analyze its timing report
Have an experience with designing an IP with on-chip interconnect protocol like AXI or AHB.
Have an experience with designing an IP with interface or protocol : PCIe, ONFI or Toggle, NVMe, DDR
Have an experience with Formal Property Verification
Experience with ECO flow

Preferred:

Deep understand issues with Coherency and Atomicity in system.
Communication and documentation skill
Experience with any Git framework