It is an American producer of computer memory and computer data storage including dynamic random-access memory, flash memory, and USB flash drives.
It is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.
s a Design Technical Lead Integration Engineer in the Non-Volatile-Engineering NAND Flash design team at organization , you will be taking a leading role in full chip-level integration activities. Your responsibility will include a floorplan, signal/power planning, full-chip schematic building, and chip-level quality checks. You will work with and support the efforts of functional teams to innovate and evaluate key multi-functional features and architecture to assure outstanding memory products in terms of die size, performance, reliability, and power. In this position, you will also work with and support the efforts of groups such as Product Engineering, Test, Probe, Quality and Reliability, Process Integration, Assembly and Marketing to proactively design products to optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will actively participate in the design and quality methodology improvements across the department. You will also be responsible for assisting product engineers in post-silicon design validation, root cause analysis, and providing solutions.
10+ years of industry experience in NAND Flash memory design
Degree/Major: BS, MS or Ph.D. in Electrical Engineering (or related fields)
Broad knowledge and experience in NAND Flash memory design is preferred
Knowledge of circuit simulators such as XA, hspice and/or hsim/finesim, etc.
An understanding of semiconductor reliability issues including CHC, NBTI, stress, and snapback, as well as Electromigration (EM) and IR analysis
An understanding of StarRC/Calibre parasitic extraction flow and capability to debug extraction issues