Location: Gurgaon/Gurugram
Salary: Open
Employment Type: Permanent

Company Overview

Looking for RTL design Engineer - World global leader organisation

Job Description

8-12 years experience
Hyderabad location
Knowledge and/or experience in large scale design projects is desirable. 

Knowledge of Digital ASIC Design methodology is required. 

Solid knowledge and experience in Verilog language. 

Knowledge and/or experience in synthesis and static timing analysis is desirable. 

Development of  NAND Flash behavioral models in SystemVerilog. 

Complete verification on  NAND Flash models based on design datasheet. 

You thoroughly understand design specs and develop verification plans for various designs. 

TestBench Development in SystemVerilog targeting complete functionality coverage. 

Support of SystemVerilog assertion and coverage-driven methodology. 

Support of design verification methodology improvements. 

Run directed and constrained-random verification tests. 

Knowledge and/or experience in non-volatile memory design (NAND in particular) is a strong plus. 

Experience with mixed-mode design and validation is a plus. 

Hands-on experience with Design/Verification CAD tools such as ncsim, Design Compiler, Formality, PrimeTime, etc. 

Knowledge and Experience with transistor level simulators such as Spice, Ultrasim, HSIM is desirable. 

Knowledge of TCL, PERL or Python is a plus.

Job reference: JO-201110-228796

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