Location: Hyderabad
Salary: Open

Company Overview

A US MNC in designing and manufacturing of chipsets for products like Flash, RAM, ROM

Job Description

The R&D group is responsible for developing state of the art high density NAND memory technologies. As a Mask Generator Engineer within this organization you will be chartered with defining, generating and maintaining mask data for current and future NAND technologies.

You will be responsible for developing a generator code to generate final mask data from drawn base layer data. You will use this code to build all masks for the development of new technology from initial development to production ramp. All mask data should be generated in a timely manner and error-free. Successful candidates for this position will have:

You will be working on software development projects that will improve the quality and efficiency of the business process and software tools.

Requirements:
Fundamental understanding of semiconductor device physics and silicon processing sub 0.1um.
Strong understanding of design rules, and the device physics and processing issues that control them.
Proven knowledge of computer programming and software: UNIX/Linux system, Python, Perl, Shell script, C/C++, SQL.
Intimate knowledge of appropriate CAD tools: Cadence df2/SKILL/K2view, Calibre/SVRF/TVF/TCL.
The familiarity of layout issues associated with high-density memories, electrical test structures, process monitors and alignment related structures.
The ability to interface with a wide variety of people with different skill sets to design, process, process integration, OPC, layout CAD.
The capability to supply innovative solutions to fix complex problems relating to the generation of mask data.
Preferred qualifications:

Fundamental understanding of CMOS operation and silicon processing sub 0.1um.
Understanding of design rules, and basic processing issues that control them.
The familiarity of layout issues associated with high-density memories, electrical test structures, process monitors and alignment related structures.
Experience: 10+ years of experience in the semiconductor industry.

Education:
Bachelor’s and 12+ years or Master’s and 10+ years of experience.

Job reference: JO-201116-229030

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