Principle Engineer- RTL Verification

A US MNC leading in chipset desgn and manufacturing for devices like storage, RAM, ROM

The Principal Design Engineer will be core technical individual contributor in design and validation of the on-chip controller and mixed signal circuitry in NAND FLASH chips. In this highly visible and challenging role, your responsibilities will include architecture development and product definition, system integration and full-chip and block-level validation plan and execution. Also RTL design and implementation of the controller hardware, synthesis, APR and full timing closure as well as development of firmware code for NAND internal operations. You will be working very closely with design teams both domestic and overseas on different projects.

Minimum Qualifications:

Able to lead/mentor the team 
Knowledge and/or experience in large scale design projects is desirable.
Knowledge of Digital ASIC Design methodology is required.
Solid knowledge and experience in Verilog language.
Knowledge and/or experience in synthesis and static timing analysis is desirable.
Knowledge and/or experience in non-volatile memory design (NAND in particular) is a strong plus.
Experience with mixed-mode design and validation is a plus.
Hands-on experience with Design/Verification CAD tools such as ncsim, Design Compiler, Formality, PrimeTime, etc.
Knowledge and Experience with transistor level simulators such as Spice, Ultrasim, HSIM is desirable.
Knowledge of TCL, PERL or Python is a plus.
MS degree in Electrical Engineering or BS + 10 years’ experience required.